The present invention relates generally to integrated circuit devices. More particularly, the invention provides a method and structure for a non-volatile memory device, commonly called a metal oxide-nitride-oxide on silicon (“MONOS”) memory device. Merely by way of example, the present invention provides a method for processing a cell region of the MONOS memory separately while protecting peripheral regions of the device for efficiency and improvement in device characterization. The peripheral regions are then processed while protecting the cell region in other embodiments. Certain steps are performed to process both the peripheral and cell region for efficiency and improved process integration purposes.
Integrated circuits proliferated through the years. Certain types of integrated circuits include memory devices. The memory devices include volatile memories such as dynamic random access memory devices, commonly called “DRAMs” and non-volatile memory devices. The nonvolatile memory device is often capable of storing data when the power supply is turned off. An example of the non-volatile memory device is a Flash Memory Device. The Flash Memory Device includes a silicon floating polysilicon gate that stores electrical charges in the floating gate. Electrons are injected onto the floating gate by channel hot electron to program the Flash memory device. Such electrons are removed from the floating gate by a tunneling influence between the floating gate and the substrate. Other types of non-volatile memory devices also exist.
Another example of non-volatile memory device is a Metal Oxide Nitride Oxide Silicon memory, which is commonly termed “MONOS.” The MONOS memory includes an MOS transistor in which the gate dielectric is a composite oxide-nitride-oxide layer. Electrons are introduced by hot electron injection into the ONO gate dielectric and stored in traps in the nitride layer of the ONO gate dielectric to program the device. The electrons are removed from the traps by a tunnel-assisted hot hole injection process. In a certain type of MONOS memory, the electrical charges are stored in traps separately at each of the edges of the transistor gate, resulting in two bits of storage in a single memory transistor.
An improved MONOS memory device incorporates two additional control gates, i.e., one at each side of the transistor gate. An example of such improved MONOS device as shown in FIG. 1, which is two bits per cell twin MONOS memory device proposed by Halo LSI Design & Device Technology, Inc. As can be seen in FIG. 1, memory cell 100 includes two control gates 20 and 30 formed on either side of the word gate 14. Insulating layer 24 separating control gate 20 from the word gate 14 and the substrate is the oxide-nitride-oxide layer where charges will be stored in the memory device. Another insulating layer 26 separates control gate 30 from the word gate 14 and the substrate. Other integrated circuit device elements are also included.
That is, impurity layers form the source and drain regions of this memory device. Two MONOS elements are formed in memory device 100 and are controlled separately by control gates 20 and 30. The MONOS device also includes word gate and buried bit line implant. Fabrication of this type of MONOS device has many challenges, such as spacer etch to form the control gates, diffusion bit line isolation, contact formation, word line formation, and integration of the cell area and the peripheral area, etc. Therefore, there is a need for an improved method for fabricating the twin MONOS memory device.
From the above, it is seen that improved manufacturing techniques for MONOS memory devices are desirable.